(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the alignment of AlCu pads as part of the copper metalization process.
(2) Description of the Prior Art
In the design and manufacturing of semiconductor devices, techniques of Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) are used to create complex semiconductor devices on the surface of a silicon substrate. Improved device performance is typically made possible by reducing device dimensions, present day technology is reaching device dimensions in the deep sub-micron range down to 0.1 xcexcm. To create device features that are part of semiconductor devices, the technique of photolithography is frequently applied. Using this technology device features or device patterns are transferred from a (relatively large dimensional) reticle or photomask to a target surface that is typically the surface of a semiconductor substrate. Step-and-repeat processes allow for the step-wise or gradual transfer of a relatively large dimensional image to ever smaller reproductions of this image to the point where the desired, if needed sub-micron, dimensions of the semiconductor device are reached.
In the process of device feature or pattern exposure, the alignment between successive layers that are being created is of critical importance. Smaller device dimensions place even more stringent requirements on the accuracy of the alignment of the successive layers that are superimposed on each other. Alignment marks that are provided in the lower layers of exposure or typically in the surface of the substrate are in this used to assure alignment between the various layers or patterns that are created. It is clear that device manufacturing yield is directly dependent on how accurate the patterns of the successive layers that make up the device are aligned. Any misalignment can result in for instance interconnect line opens or shorts or shorts or high leakage currents between adjacent regions within a device. Several alignment marks can be provided per wafer, each alignment mark having a specific function such as wafer positioning, contact etching or photoresist patterning. Alignment marks are mostly incorporated into the chip and are placed close to the edge of the wafer. The process of using alignment marks makes use of the step height of the alignment marks. By etching a depth into the surface of a substrate, a step height of the alignment mark is created. Wafer positioning is performed, typically by a wafer stepper tool, to assure proper alignment of a pattern that is to be created in a deposited layer with the pattern of the preceding layer. When performing this wafer alignment, the surface of the (underlying) layer that has been provided with alignment marks is coated with a transparent layer of photoresist. A laser light beam is aimed at the alignment mark, light will be reflected by the alignment mark and provides in this manner an exact indication of the position of the wafer in the stepper tool. This allows the stepper tool to adjust the wafer position to the desired position, making accurate alignment between overlying layers possible. Each photomask that is used for the exposure of the various layers that make up the semiconductor device is provided with alignment marks, which allow for accurate alignment of all photomasks that are used for the creation of the device. During this process, the alignment mark is replicated in the overlying layer and in this manner migrates upward with the successive layers that are being formed. This leads to problems where layers of for instance interconnect metal need to be planarized, thereby potentially erasing the alignment mark. Before the layer of interconnect metal is deposited, the dielectric (Intra-Level Dielectric or ILD) is planarized for reasons of satisfactory metal deposition. This planarization removes the underlying alignment mark, making alignment for the interconnect metal difficult to achieve. In another typical processing sequence, metal interconnects or vias are created in a layer of dielectric or insulation. The metal that is used to fill the interconnects or vias is then deposited over the surface of the dielectric or insulation thereby filling the openings that have been created for the vias. The excess metal is removed from the surface of the dielectric, typically using CMP technology, a process that results in a smooth surface of the layer of dielectric and which eliminates the (required) sharply defined edges of the alignment marks and makes the alignment of overlying layers very difficult. Additional processing steps may in these cases be required in order to restore the visibility of the alignment marks, these additional processing steps add to the cost of the overall device and are therefore to be avoided whenever possible. One of the techniques that is used for this purpose is the creation of the xe2x80x9copen framexe2x80x9d whereby the step height of the original mark is recreated.
FIGS. 1a and 1b show a Prior Art process of using alignment marks for the creation of an AlCu pad in an overlying layer. The contact points 12 are points of electrical interconnect that have been created in an underlying layer 10. It is the objective of the process that is highlighted in FIGS. 1a and 1b to create an AlCu pad that overlays and makes contact with at least one of the electrical contact points 12. Alignment marks 20 are present in an underlying layer and are used for both the alignment of the contact points 12 and for the alignment of the to be created and overlying AlCu pad.
The processing flow that is shown in FIGS. 1a and 1b can be summarized as follows in the sequence listed, assuming that the pattern 12 of electrical points of contact has been created in layer 10:
deposit a layer 14 of passivation
pattern the layer 14 of passivation for opening 16
sputter deposit a layer 18 of AlCu
perform photo exposure and etch for the alignment marks 20 thereby making the alignment marks 20 visible, and
perform photo exposure and etch for the AlCu pad.
It must be emphasized that, in the above indicated processing sequence, the photo and etch sequence for the alignment marks are first performed as one processing sequence followed by another processing sequence of photo and resist for the AlCu pad. The first of these two steps, that is the photo and etch steps for the alignment marks 20, is necessary because the alignment marks 20 are not visible through the layer 14 of passivation and layer 18 of AlCu and can therefore not be used as alignment marks for the photo and etch of the AlCu pad that is to be created.
The AlCu pad is to be created over at least one of the points of electrical contact of copper 12 that have been created in the surface of, for instance, a substrate 10. A layer 14 of passivation has been deposited over a surface of layer 10, layer 10 can be the surface of a semiconductor substrate or it can be a layer of dielectric. The layer 14 of passivation has been patterned thereby creating opening 16 (for the AlCu pad) in this layer 14 of passivation whereby opening 16 aligns with at least one of the electrical contact points of copper pattern 12. A layer 18 (FIG. 1b) of AlCu is sputter deposited over the layer 14 of passivation thereby including the opening 16 that has been created in the layer 14 of passivation. Alignment marks 20 have been shown as being present but as being located at a level below the surface of layer 10. The creation of opening 16 required an alignment of the photolithographic mask whereby the mask is aligned using the alignment marks 20, the creation of the AlCu that overlays at least one of the electrical points of contact 12 requires an alignment of a photolithographic mask using the same alignment marks 20. This alignment assumes that the light that is used to perform the process of alignment can penetrate the layer 14 of passivation in addition to the sputter deposited layer 18 of AlCu. The layers 14 of passivation and 18 of AlCu are however opaque and light can therefore not readily penetrate through these layers, making the photolithographic alignment for the AlCu pad difficult and cumbersome. To improve the alignment for the creation of the AlCu pad, the alignment marks 20 must be made visible requiring an extra processing sequence of photolithographic exposure and etch whereby the location that aligns with the alignment marks 20 is opened. These processing steps of photo exposure and etch of the layer 18 of AlCu require Wide Clear Window (WCW) mask layer exposure followed by etch of layers 18 and 14. This latter processing sequence removes layers 18 and 14 from above the alignment marks 20, the alignment marks 20 can then be used to perform the exact photolithographic exposure and etch for the AlCu pad that is in exact alignment with the copper pattern 12. The invention teaches a method of forming an AlCu pad in an environment of copper interconnect lines that can be readily integrated into the regular processing stream. The process of forming the AlCu pad is aimed at creating alignment pads but can possibly be extended to bond pads or any other large surface area on the surface of a semiconductor substrate.
U.S. Pat No. 5,872,042 (Hsu et al.) (TSMC) shows a method for regenerating an alignment mark by etching alignment marks using same photo etch step as the via or contact hole. This patent is very close to the invention. This patent differs from the invention in that the invention etches alignment marks in a passivation layer in contrast with Hsu that etches alignment mark in an IMD layer.
U.S. Pat. No. 5,933,744 (Chen et al.) teaches an alignment mark process used in a chemical-mechanical polish step.
U.S. Pat. No. 5,897,371 (Yeh et al.) teaches an alignment mark process that is compatible with a chemical-mechanical polish process.
A principle objective of the invention is to provide a method for AlCu pad alignment that is readily integratable in semiconductor manufacturing processes.
Another objective of the invention is to reduce the number of processing steps that is required to accurately align the patterning of AlCu pads.
In accordance with the objectives of the invention a new method is provided for the alignment of the patterning of AlCu pads in an environment of copper interconnect line patterns. A layer of passivation material is deposited over the surface that contains alignment marks. The layer of passivation is patterned creating in the surface of the layer of passivation the opening that is required for the AlCu pad in addition to openings for a new pattern of alignment marks. A layer of AlCu is sputter deposited over the surface of the layer of passivation thereby including the openings that have been created in the layer of passivation. This creates a new pattern of alignment marks in the surface of the deposited layer of AlCu whereby these new alignment marks align with the pattern of new alignment marks that has been etched in the layer of passivation. The new alignment marks are then used to pattern the layer of AlCu for the creation of the AlCu pad.